Motorola CPU32 Reference Manual page 279

III
sensitive means that the level seven input must change state before the CPU
will detect an interrupt.
An NMI is generated each time the interrupt request level changes to level
seven (regardless of priority mask value), and each time the priority mask
changes from seven to a lower number while request level remains at seven.
Many M68000 peripherals provide for programmable interrupt vector numbers
to be used in the system interrupt request/acknowledge mechanism. If the
vector number is not initialized after reset and if the peripheral must
acknowledge an interrupt request, the peripheral should return the uninitialized
interrupt vector number (15).
See the system integration user's manual for detailed information on interrupt
acknowledge cycles.
6.2.12 Return from Exception
When exception stacking operations for all pending exceptions are complete,
the processor begins execution of the handler for the last exception processed.
After the exception handler has executed, the processor must restore the
system context in existence prior to the exception. The RTE instruction is
designed to accomplish this task.
When RTE is executed, the processor examines the stack frame on top of the
supervisor stack to determine if it is valid and determines what type of context
restoration must be performed. See 6.4 CPU32 Stack Frames for a
description of stack frames.
For a normal four-word frame, the processor updates the status register and
program counter with data pulled from the stack, increments the supervisor
stack pOinter by eight, and resumes normal instruction execution. For a six-
word frame, the status register and program counter are updated from the stack,
the active supervisor stack pOinter is incremented by 12, and normal instruction
execution resumes.
For a bus fault frame, the format value on the stack is first checked for validity. In
addition, the version number on the stack must match the version number of the
processor that is attempting to read the stack frame. The version number is
located in the most significant byte (bits [15:8]) of the internal register word at
location SP
+
$14 in the stack frame. The validity check insures that stack frame
data will be properly interpreted in multiprocessor systems.
If a frame is invalid, a format error exception is taken. If it is inaccessible, a bus
error exception is taken. Otherwise, the processor reads the entire frame into
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EXCEPTION PROCESSING CPU32 REFERENCE MANUAL