Motorola CPU32 Reference Manual page 81

M68300 series central processor unit
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III
ADDQ
Add Quick
ADDQ
Instruction Fields:
Data field - Three bits of immediate data, (9-11), with 0 representing a value of 8).
Size field - Specifies the size of the operation:
00 -
Byte operation
01 - Word operation
10 -
Long operation
Effective Address field -
Specifies the destination location.
Only alterable addressing modes are allowed as shown:
Addressing Mode
Mode
Register
Addressing Mode Mode
On
000
Reg. number: On
(xxx).W
111
An*
001
Reg. number: An
(xxx).L
111
(An)
010
Reg. number: An
#(data)
111
(An)
+
011
Reg. number: An
-(An)
100
Reg. number: An
(d16, An)
101
Reg. number: An
(d16, PC)
111
(de, An, Xn)
110
Reg. number: An
(de, PC, Xn)
111
(bd, An, Xn)
110
Reg. number: An
(bd, PC, Xn)
111
*Word and long only
Register
000
001
100
010
011
011
MOTOROLA
4-28
INSTRUCTION SET
CPU32 REFERENCE MANUAL

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