Motorola CPU32 Reference Manual page 104

BSR
Branch to Subroutine BSR
Operation:
Assembler
Syntax:
Attributes:
SP - 4
=>
SP; PC
=>
(SP); PC
+
d
=>
PC
BSR (label)
Size
=
(Byte, Word, Long)
Description:
Pushes the long word address of the instruction immediately following the BSR
instruction onto the system stack. The PC contains the address of the instruction word plus two.
Program execution then continues at location (PC)
+
displacement. The displacement is a twos
complement integer that represents the relative distance in bytes from the current PC to the
destination PC. If the 8-bit displacement field in the instruction word is zero, a 16-bit displacement
(the word immediately following the instruction) is used. If the 8-bit displacement field in the
instruction word is all ones ($FF), the 32-bit displacement (long word immediately following the
instruction) is used.
Condition Codes:
Not affected.
Instruction Format:
15 14 13 12 11
10 9
8
7 6 5 4
3
2
o
0
I
1
I
1
I
o
I
o
I
o
I
o
I
1
I
8-BIT DISPLACEMENT
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT
=
$00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
Instruction Fields:
8-Bit Displacement field - Twos complement integer specifying the number of bytes between
the branch instruction and the next instruction to be executed.
16-Bit Displacement field - Used for larger displacement when 8-bit displacement is $00.
32-Bit Displacement field - Used for larger displacement when 8-bit displacement is $FF.
NOTE
A branch to the instruction immediately following automatically uses 16-bit
displacement because the 8-bit displacement field contains $00 (zero offset).
CPU32 REFERENCE MANUAL INSTRUCTION SET MOTOROLA
4-51