Motorola CPU32 Reference Manual page 286

There are three varieties of Type III operand fault recovery. The first is
completion of an instruction in software. The second is conversion to Type II
with restart via RTE. The third is continuation from the fault via RTE.
6.3.2.1 (Type I) Completing Released Writes via Software
To complete a bus cycle in software, a handler must first read the SSW function
code field to determine the appropriate address space, then access the fault
address pOinter on the stack, and then transfer data from the stacked image of
the output buffer to the fault address.
Because the CPU32 has a 16-bit internal data bus, long operands require two
bus accesses. A fault during the second access of a long operand causes the
LG bit in the SSW to be set. The SIZ field indicates remaining operand size. If
operand coherency is important, the complete operand must be rewritten. After
a long operand is rewritten, the RR bit must be cleared. Failure to clear the RR
bit can cause RTE to rerun the bus cycle. Following rewrite, it is not necessary
to adjust the program counter (or other stack contents) before executing RTE.
6.3.2.2 (Type I) Completing Released Writes via RTE
An exception handler can use the RTE instruction to complete a faulted bus
cycle. When RTE executes, the fault address, data output buffer, program
counter, and status register are restored from the stack. Any pending
breakpoint or trace exceptions, as indicated by TR, B1, and 80 in the stacked
SSW, are requeued during SSW restoration. The RR bit in the SSW is checked
during the unstacking operation - if it is set, the RW, FUNC, and SIZ fields are
restored and the released write cycle is rerun.
To maintain long-word operand coherence, stack contents must be adjusted
prior to RTE execution. The fault address must be decremented by two if LG is
set and SIZ indicates a remaining byte or word. SIZ must be set to long. All
other fields should be left unchanged. The bus controller uses the modified
fault address and SIZ field to rerun the complete released write cycle
Manipulating the stacked SSW can cause unpredictable results because RTE
checks only the RR bit to determine if a bus cycle must be rerun. Inadvertent
alteration of the control bits could cause the bus cycle to be a read instead of a
write, or could cause access to a different address space than the original bus
cycle. If the rerun bus cycle is a read, returned data will be ignored.
CPU32 REFERENCE MANUAL EXCEPTION PROCESSING
MOTOROLA
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