Block Diagram - Motorola CPU32 Reference Manual

III
1.2 Block Diagram
A block diagram of the CPU32 is shown in Figure 1-2. The functional elements
operate concurrently. Essential synchronization of instruction execution and
bus operation is maintained by the sequencer/control unit. The bus controller
prefetches instructions and operands. A three-stage pipeline is used to hold
and decode instructions prior to execution. The execution unit maintains the
program counter and performs required operations under sequencer control.
The bus control contains a write-pending buffer that allows the sequencer to
continue execution of instructions after a request for a write cycle is queued.
See SECTION 8 INSTRUCTION EXECUTION TIMING for a detailed
explanation of instruction execution.
DATA BUS
ADDRESS
BUS
MOTOROLA
1-8
SEQUENCER
CONTROL
UNIT
INSTRUCTION
PIPELINE
AND
DECODE
BUS
CONTROL
CPU32 Block Diagram
BUS CONTROL
OVERVIEW
CPU32 REFERENCE MANUAL