Motorola CPU32 Reference Manual page 13

Figure
Number
7-8
7-9
7-10
7-11
7-12
8-1
8-2
8-3
8-4
8-5
8-6
8-7
MOTOROLA
xii
LIST OF ILLUSTRATIONS (Continued)
Title
Page
Number
BKPT Timing for Forcing BDM .................................................................. 7-12
BKPT/DSCLK Logic Diagram ................................................................... 7-12
Command-Sequence-Diagram Example .............................................. 7-15
Functional Model of Instruction Pipeline ................................................ 7-34
Instruction Pipeline Timing Diagram ....................................................... 7-35
Block Diagram of Independent Resources ............................................ 8-2
Simultaneous Instruction Execution ........................................................ 8-4
Attributed Instruction Times ....................................................................... 8-5
Example 1 - Instruction Stream ............................................................. 8-8
Example 2 - Branch Taken ..................................................................... 8-8
Example 2 - Branch Not Taken .............................................................. 8-9
Example 3 - Branch Negative Tail ........................................................ 8-10
CPU32 REFERENCE MANUAL