Registers - Motorola CPU32 Reference Manual

2.2 Registers
Registers D7 to DO are used as data registers for bit, byte (8-bit), word (16-bit),
long-word (32-bit), and quad-word (64-bit) operations. Registers A6 to AO and
the user and supervisor stack pointers are address registers that may be used
as software stack painters or base address registers. Register A7 (shown as A7
and AT in Figure 2-1) is a register designation that applies to the user stack
pointer in the user privilege level and to the supervisor stack pointer in the
supervisor privilege level. In addition, address registers may be used for word
and long-word operations. All of the 16 general-purpose registers (D7 to DO,
A7 to AO) may be used as index registers.
The program counter (PC) contains the address of the next instruction to be
executed by the CPU32. During instruction execution and exception
processing, the processor automatically increments the contents of the PC or
places a new value in the PC, as appropriate.
The status register (SR) (see Figure 2-3) contains condition codes, an interrupt
priority mask (three bits), and three control bits. Condition codes reflect the
results of a previous operation. The codes are contained in the low byte, or
condition code register of the SA. The interrupt priority mask determines the
level of priority an interrupt must have in order to be acknowledged. The control
bits determine trace mode and privilege level. At user privilege level, only the
condition code register is available. At supervisor privilege level, software can
access the full status register.
SYSTEM BYTE
USER BYTE
(CONDITION CODE REGISTER)
~
_ _ _ _ _ _ _ _ _ _
~A~
_ _ _ _ _ _ _ _ _ _ _ _ _
v~
____________
~A~
_ _ _ _ _ _ _ _ _ _ _ _
SUPERVISOR / USER
STATE
CPU32 REFERENCE MANUAL
Figure 2-3. Status Register
ARCHITECTURE SUMMARY
NEGATIVE
ZERO CARRY
OVERFLOW
MOTOROLA
2-3