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M68000 Family members. The only internal machine state required in the
CPU32 stack frame is the bus controller state at the time of the error, and a
single register.
Bus operation in progress at the time of a fault is conveyed by the SSW.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
I
1P
I
MV
I
0
I
lR
I
B1
BO
I
RR
I
AM
I
IN
I
RN
I
LG
I
SIZ
FUNC
The BERR stack frame is 12 words in length. There are three variations of the
frame, each distinguished by different va.lues in the SSW TP and MV fields.
An internal transfer count register appears at location SP
+
14 in all bus error
stack frames. The register contains an 8-bit microcode revision number, and,
for type III faults, an 8-bit transfer count. Register format is shown in Figure 6-5.
15
8
7
o
MICROCODE REVISION NUMBER
mANSFER COUNT
Figure 6-5. Internal Transfer Count Register
The microcode revision number is checked before a BERR stack frame is
restored via RTE.
In a multiprocessor system, this check insures that a
processor using stacked information is at the same revision level as the
processor that created it.
The transfer count is ignored unless the MV bit in the stacked SSW is set. If the
MV bit is set, the least significant byte of the internal register is reloaded into the
MOVEM transfer counter during RTE execution.
For faults occurring during normal instruction execution (both prefetches and
non-MOVEM operand accesses) SSW [TP:MV]
=
00. Stack frame format is
shown in Figure 6-6.
Faults that occur during the operand portion of the MOVEM instruction.are
identified by SSW [TP:MV]
=
01. Stack frame format is shown in in Figure 6-7.
When a bus error occurs during exception processing, SSW [TP:MV]
=
10. The
frame shown in Figure 6-8 is written below the faulting frame. Stacking begins
MOTOROLA
6-28
EXCEPTION
PROCESSING
CPU32 REFERENCE MANUAL
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