Motorola CPU32 Reference Manual page 304

Both OSCLK and DSI are synchronized to on-chip clocks, thereby minimizing
the chance of propagating metastable states into the serial state machine. Data
is sampled during the high phase of CLKOUT. At the falling edge of CLKOUT,
the sampled value is made available to internal logic.
If
there is no
synchronization between CPU32 and development system hardware, the
minimum hold time on OSI with respect to OSCLK is one full period of CLKOUT.
CLKOUT
FREEZE
~
DSCLK
I
DSI
SAMPLE
~ ~ ~ ~ ~
WINDOW
INTERNAL
SYNCHRONIZED
DSCLK
INTERNAL
SYNCHRONIZED
DSI
DSO
CLKOUT
Figure 7-6. Serial Interface Timing Diagram
The serial state machine begins a sequence of events based on the rising edge
of the synchronized OSCLK (see Figure 7-6). Synchronized serial data is
transferred to the input shift register, and the received bit counter is
decremented. One-half clock period later, the output shift register is updated,
bringing the next output bit to the OSO signal. DSO changes relative to the
rising edge of OSCLK and does not necessarily remain stable until the falling
edge of OSCLK.
CPU32 REFERENCE MANUAL
DEVELOPMENT SUPPORT
MOTOROLA
7-11