Motorola CPU32 Reference Manual page 124

DIVS
DIVSL
Operation:
Assembler
Syntax:
Attributes:
Signed Divide
Destination / Source
~
Destination
DIVS.W {ea), Dn
DIVS.L {ea), Dq
DIVS.L {ea), Dr:Dq
DIVSL.L {ea), Dr:Dq
Size
=
(Word, Long)
32/16 ==> 16r: 16q
32/32 ~ 32q
64/32
==>
32r:32q
32/32
==>
32r:32q
DIVS
DIVSL
Description: Divides the signed destination operand by the signed source operand and stores the
signed result in the destination. The instruction uses one of four forms.
The word form of the instruction divides a long word by a word. The result is a quotient in the
the destination. The sign of the remainder is the same as the sign of the dividend. •
lower word (least significant 16 bits) and a remainder in the upper word (most significant 16 bits) of
III
The first long form divides a long word by a long word. The result is a long quotient; the remainder
is discarded.
The second long form divides a quad word (in any two data registers) by a long word. The result is
a long word quotient and a long word remainder.
The third long form divides a long word by a long word. The result is a long word quotient and a
long word remainder.
Two special conditions may arise during the operation:
1. Division by zero causes a trap.
2. Overflow may be detected before instruction completion. If an overflow is detected, the
overflow condition code is set and the operands are unaffected.
CPU32 REFERENCE MANUAL INSTRUCTION SET MOTOROLA
4-71