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III
8.3.3 MOVE Instruction
The MOVE instruction table indicates the number of clock periods needed for
the processor to calculate the destination effective address and to perform a
MOVE or MOVEA instruction.
For entries with CEA or FEA, refer to the
appropriate table to calculate that portion of the instruction time.
Destination effective addresses are divided by their formats (refer to 3.4.4
Effective Address Encoding Summary). The total number of clock cycles
is outside the parentheses.
The numbers inside parentheses (r/p/w) are
included in the total clock cycle number. All timing data assumes two-clock
"reads and writes.
When using this table, begin at the top and move downward. Use the first entry
that matches both source and destination addressing modes.
Instruction
Head
Tall
Cycles
MOVE Rn, Rn
0
0
2(0/1/0)
MOVE (FEA), Rn
0
0
2(0/1/0)
MOVE Rn, (Am)
0
2
4(0/1/x)
MOVE Rn, (Am)+
1
1
5(0/1/x)
MOVE Rn, -(Am)
2
2
6(0/1/x)
MOVE Rn, (CEA)
1
3
5(0/1/x)
MOVE (FEA), (An)
2
2
6(0/1/x)
MOVE (FEA), (An)+
2
2
6(0/1/x)
MOVE (FEA), -(An)
2
2
6(0/1/x)
MOVE #, (CEA)
2
2
6(0/1/x)*
MOVE (CEA), (FEA)
2
2
6(0/1/x)
X
=
There is one bus cycle for byte and word operands and two bus cycles for long
operands. For long bus cycles, add two clocks to the tail and to the number of
cycles.
*An # fetch effective address time must be added for this instruction:
(FEA) +(CEA) + (OPER)
NOTE: For instructions not explicitly listed, use the MOVE (CEA), (FEA) entry. The source
effective address is calculated by the calculate effective address table, and the
destination effective address is calculated by the fetch effective address table,
even though the bus cycle is for the source effective address.
8.3.4 Special-Purpose MOVE Instruction
The special-purpose MOVE instruction table indicates the number of clock
periods needed for the processor to fetch, calculate, and perform the special-
purpose MOVE operation on control registers or a specified effective address.
MOTOROLA
8-16
INSTRUCTION EXECUTION
CPU32 REFERENCE MANUAL
TIMING
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