Enhanced Addressing Modes - Motorola CPU32 Reference Manual

III
Because the VBR stores the vector table base address, the table can be located
anywhere in memory. It can also be dynamically relocated for each task
executed by an operating system. Details of exception processing are provided
in SECTION 6 EXCEPTION PROCESSING.
1.1.4 Exception Handling
The processing of an exception occurs in four steps, with variations for different
exception causes. During the first step, a temporary internal copy of the status
register is made, and the status register is set for exception processing. During
the second step, the exception vector is determined. During the third step, the
current processor context is saved. During the fourth step, a new context is
obtained, and the processor then proceeds with normal instruction execution.
Exception processing saves the most volatile portion of the current context by
pushing it on the supervisor stack. This context is organized in a format called
the exception stack frame. The stack frame always includes the status register
and program counter at the time an exception occurs. To support generic
handlers, the processor also places the vector offset in the exception stack
frame and marks the frame with a format code. The return-from-exception (RTE)
instruction uses the format code to determine what information is on the stack,
so that context can be properly restored.
1.1.5 Enhanced Addressing Modes
Addressing in the CPU32 is register oriented. Most instructions allow the
results of the specified operation to be placed either in a register or in memory.
There is no need for extra instructions to store register contents in memory.
There are seven basic addressing modes:
1. Register Direct
2. Register Indirect
3. Register Indirect with Index
4. Program Counter Indirect with Displacement
5. Program Counter Indirect with Index
6. Absolute
7. Immediate
The register indirect addressing modes include postincrement, predecrement,
and offset capability. The PC relative mode also has index and offset
capabilities. In addition to the addressing modes, many instructions implicitly
specify the use of status register, SP, and/or PC. Addressing is explained fully
in SECTION 3 ADDRESSING MODES. A summary of M68000 Family
addressing modes is found in APPENDIX A M68000 FAMILY SUMMARY.
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