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III
four fault types: released write faults, faults during exception processing, faults
during MOVEM operand transfer, and faults on any other bus cycle.
6.3.1.1 Type I: Released Write Faults
CPU32 instruction pipelining can cause a final instruction write to overlap the
execution of a following instruction.
A write that is overlapped is called a
released write. Since the machine context for the instruction that queued the
write is lost as soon as the following instruction starts, it is impossible to restart
the faulted instruction.
Released write faults are taken at the next instruction boundary. The stacked
program counter is that of the next unexecuted instruction. If a subsequent
instruction attempts an operand access while a released write fault is pending,
the instruction is aborted and the write fault is acknowledged. This action
prevents stale data from being used by the instruction.
The SSW for a released write fault contains the following bit pattern:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
I
a
I
a
I
0
I
1R
I
B1
I
BO
I
1
I
a
I
a
I
a
I
LG
I
SIZ
FUNC
TR, B1, and BO are set if the corresponding exception is pending when the
BERR exception is taken. Status regarding the faulted bus cycle is reflected in
the SSW LG, SIZ, and FUNC fields.
The remainder of the stack contains the program counter of the next unexecuted
instruction, the current status register, the address of the faulted memory
location, and the contents of the data buffer which was to be written to memory.
This data is written on the stack in the format depicted in Figure 6-3.
6.3.1.2 Type II: Prefetch, Operand, RMW, and MOVEP Faults
The majority of BERR exceptions are included in this category -
all instruction
prefetches, all operand reads, all RMW cycles, and all operand accesses
resulting from execution of MOVEP (except the last write of a MOVEP Rn,(ea) or
the last write of MOVEM, which are type I faults). The TAS, MOVEP, and
MOVEM instructions account for all operand writes not considered released.
All type II faults cause an immediate exception that aborts the current instruction
Any registers that were altered as the result of an effective address calculation
(i.e., postincrement or predecrement) are restored prior to processing the bus
cycle fault.
MOTOROLA
6-20
EXCEPTION
PROCESSING
CPU32 REFERENCE MANUAL
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