Motorola CPU32 Reference Manual page 273

The vector number for the TRAP instruction is internally generated - part of the
number comes from the instruction itself. The trap 'lector number, program
counter value, and a copy of the status register are saved on the supervisor
stack. The saved program counter value is the address of the instruction that
follows the instruction which generated the trap. For all instruction traps other
than TRAP, a pointer to the instruction causing the trap is also saved in the fifth
and sixth words of the exception stack frame.
6.2.5 Software Breakpoints
To support hardware emulation, the CPU32 must provide a means of inserting
breakpoints into target code and of announcing when a breakpoint is reached.
The MC68000 and MC68008 can detect an illegal instruction inserted at a
breakpoint when the processor fetches from the illegal instruction exception
vector location. Since the VBR on the CPU32 allows relocation of exception
vectors, the exception vector address is not a reliable indication of a breakpoint.
CPU32 breakpoint support is provided by extending the function of a set of
illegal instructions ($4848 - $484F).
When a breakpoint instruction is executed, the CPU32 performs a read from
CPU space $0, at a location corresponding to the breakpoint number (See 5.3
Types of Address Space). If this bus cycle is terminated by BERR, the
processor performs illegal instruction exception processing. If the bus cycle is
terminated by DSACK, the processor uses the data returned to replace the
breakpoint in the instruction pipeline and begins execution of that instruction.
6.2.6 Hardware Breakpoints
The CPU32 recognizes hardware breakpoint requests. Hardware breakpoint
requests do not force immediate exception processing, but are left pending. An
instruction breakpoint is not made pending until the instruction corresponding to
the request is executed.
A pending breakpoint can be acknowledged between instructions or at the end
of exception processing. To acknowledge a breakpoint, the CPU performs a
read from CPU space $0 at location $1 E. See 5.3 Types of Address Sp,ace
for a detailed description of CPU space operations.
If the bus cycle terminates normally, instruction execution continues with the
next instruction, as if no breakpoint request occurred. If the bus cycle is
terminated by BERR, the CPU begins exception processing. Data returned
during this bus cycle is ignored.
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EXCEPTION PROCESSING CPU32 REFERENCE MANUAL