Motorola CPU32 Reference Manual page 363

References,
Data, 3-2
Implicit, 3-3
Program, 3-2
Register Direct Mode, 3-4
Registers,
Address, 2-6
Condition Code, 2-3, 4-6
Control, 2-6
Data, 2-4
Function Code, 2-4
Organization, 2-3
Status, 2-3
Vector Base, 2-4, 6-1
Released Writes, 6-20, 6-23
Reset, 6-6
Resource Scheduling, 8-1
Return from Exception, 6-16
Rotate Instructions, 4-12
- s -
Save and Restore Operation Timing, 8-28
Serial Interface (BDM), 7-8
Shift and Rotate Instructions, 4-12
Shift and Rotate Instruction Timing, 8-23
Single Operand Instruction Timing, 8-22
Six-Word Stack Frame, Normal, 6-27
Sizing, Dynamic Bus, 6-19, 6-29
Software Breakpoints, 6-10
Software Fault Recovery, 6-23ff
Space Formats, 5-5
Type 0000 - Breakpoint, 5-5
Type 0001 - MMU Access, 5-5
Type 0010 - Coprocessor Access, 5-5
Type 0011 -Internal Register Access, 5-5
Type 1111 - Interrupt Acknowledge, 5-6
Special Addressing Modes, 3-8
Special-Purpose MOVE Instruction Timing, 8-16
Stack,
Frames, 6-4, 6-26
User, 2-3, 3-19
Supervisor, 2-3, 3-19
System, 3-20
State Transition, 5-1
Status Register, 2-3
Subroutine Calls, Nested, 4-203
Supervisor Privilege Level, 5-2
Surface Interpolation, 4-195, 4-203
System,
Control Instructions, 4-15
Stack,3-20
Synchronization, Pipeline with NOP, 4-203
MOTOROLA
4
INDEX
- T -
Table Lookup and Interpolation, 4-195
Examples,
Standard Usage, 4-196
Compressed Table, 4-197
8-Bit Independent Variable, 4-199
Maintaining Precision, 4-201
Surface Interpolations, 4-203
Instruction, Using the, 4-192
Tests, Condition, 4-17
Timing Examples,
Execution Overlap, 8-8
Branch Instructions, 8-9
Negative Tails, 8-10
Timing Tables, 8-11
Arihmetic/Logic Instructions, 8-18
Binary-Coded Decimal/Extended Instructions, 8-21
Bit Manipulation Instructions, 8-24
Calculate Effective Address (CEA), 8-15
Conditional Branch Instructions, 8-25
Control Instructions, 8-26
Exception-Related Instructions, 8-27
Fetch Effective Address (FEA), 8-14
Immediate Arithmetic/Logic Instructions, 8-20
MOVE Instruction, 8-16
Save and Restore Operations, 8-28
Shift/Rotate Instructions, 8-23
Single Operand Instructions, 8-22
Special-Purpose MOVE Instruction, 8-17
Trace on Instruction Execution, 6-13, 7-1
-u-
Unimplemented Instruction Emulation, 6-11, 7-1
Unimplemented Instructions, 4-2, 6-11
User Privilege Level, 5-2
User Stacks, 3-20
-v-
Vector Base Register, 1-3,2-4,6-1
Vectors, Exception, 6-1
Virtual Memory, 1-2
-w-
Write Pending Buffer, 8-3
CPU32 REFERENCE MANUAL