Example Of Controlling Internal High-Speed Oscillation Clock - NEC 78K0 Series User Manual

(b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1
<1> Confirming the CPU clock status (PCC and MCM registers)
Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system
clock.
When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the
CPU clock to the subsystem clock or internal high-speed oscillation clock.
CLS MCS
0
0
1
<2> Stopping the high-speed system clock (MOC register)
When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled).
Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop
peripheral hardware that is operating on the high-speed system clock.

6.6.2 Example of controlling internal high-speed oscillation clock

The following describes examples of clock setting procedures for the following cases.
(1) When restarting oscillation of the internal high-speed oscillation clock
(2) When using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or
high-speed system clock as peripheral hardware clock
(3) When stopping the internal high-speed oscillation clock
(1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clock
<1> Setting restart of oscillation of the internal high-speed oscillation clock (RCM register)
When RSTOP is cleared to 0, the internal high-speed oscillation clock starts operating.
<2> Waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (RCM
register)
Wait until RSTS is set to 1
Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the
internal high-speed oscillation clock is selected as the CPU clock.
2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral
hardware clock.
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CHAPTER 6 CLOCK GENERATOR
0 Internal high-speed oscillation clock
1 High-speed system clock
×
Subsystem clock
Note 2
.
Preliminary User's Manual U17260EJ3V1UD
CPU Clock Status
Note 1