NEC 78K0 Series User Manual page 497

8-bit single-chip microcontrollers

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(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)

These registers specify the valid edge for INTP0 to INTP7.

EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation sets these registers to 00H.

Figure 19-5. Format of External Interrupt Rising Edge Enable Register (EGP)

Address: FF48H

After reset: 00H

Address: FF49H

After reset: 00H

Table 19-3 shows the ports corresponding to EGPn and EGNn.

Detection Enable Register

Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be

detected when the external interrupt function is switched to the port function.

Remark n = 0 to 7

CHAPTER 19 INTERRUPT FUNCTIONS

and External Interrupt Falling Edge Enable Register (EGN)

INTPn pin valid edge selection (n = 0 to 7)

Edge detection disabled

Falling edge

Both rising and falling edges

Table 19-3. Ports Corresponding to EGPn and EGNn

Edge Detection Port

Preliminary User's Manual U17260EJ3V1UD

Interrupt Request Signal

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