NEC 78K0 Series User Manual page 234

(3) Measuring the pulse width by using one input signal of the TI00n pin (clear & start mode entered by the
TI00n pin valid edge input)
Set the clear & start mode entered by the TI00n pin valid edge (TMC0n3 and TMC0n2 = 10). The count value of
TM0n is captured to CR00n in the phase reverse to the valid edge of the TI00n pin, and the count value of TM0n
is captured to CR01n and TM0n is cleared (0000H) when the valid edge of the TI00n pin is detected. Therefore,
a cycle is stored in CR01n if TM0n does not overflow.
If an overflow occurs, take the value that results from adding 10000H to the value stored in CR01n as a cycle.
Clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0.
Figure 7-55. Timing Example of Pulse Width Measurement (3)
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture & count clear input
(TI00n)
Capture register
(CR00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
Overflow flag
(OVF0n)
Capture trigger input
(TI01n)
Capture interrupt
(INTTM00n)
<1> Pulse cycle =
<2> High-level pulse width = (10000H × Number of times OVF0n bit is set to 1 + Captured value of CR00n) ×
<3> Low-level pulse width = (Pulse cycle − High-level pulse width)
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
234
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
• TMC0n = 08H, PRM0n = 10H, CRC0n = 07H
N
M
A
00 10
<1>
<2> <3>
0000H
0000H M
L
L
(10000H × Number of times OVF0n bit is set to 1 + Captured value of CR01n) ×
Count clock cycle
Count clock cycle
Preliminary User's Manual U17260EJ3V1UD
B
S
<1> <1>
<2> <3> <2>
A B
N S
0 write clear
P Q
C D
<1>
<3> <2> <3>
C
D
Q
P
00