NEC 78K0 Series User Manual page 138

Figure 6-2. Format of Clock Operation Mode Select Register (OSCCTL)
Address: FF9FH After reset: 00H
Symbol <7>
OSCCTL EXCLK
EXCLK
0
0
1
1
AMPH
0
1
Note
Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency
Remark f
138
CHAPTER 6 CLOCK GENERATOR
R/W
<6> <5>
Note
OSCSEL EXCLKS OSCSELS
OSCSEL High-speed system clock
pin operation mode
0 I/O port mode
1 X1 oscillation mode
0 I/O port mode
1 External clock input
mode
1 MHz ≤ f ≤ 10 MHz
XH
≤ 20 MHz
10 MHz < f
XH
EXCLKS and OSCSELS are used in combination with XTSTART (bit 6 of the processor
clock control register (PCC)). See (3) Setting of operation mode for subsystem clock
pin.
exceeds 10 MHz.
2. Set AMPH before setting the peripheral functions after a reset release. The value
of AMPH can be changed only once after a reset release. The clock supply to the
µ
CPU is stopped for 5
3. If the STOP instruction is executed with AMPH set to 1 when the internal high-
speed oscillation clock or external main system clock is used as the CPU clock,
then the clock supply to the CPU is stopped for 5
has been released.
stabilization time is counted after the STOP mode has been released.
4. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7
(MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or
the external clock from the EXCLK pin is disabled).
: High-speed system clock oscillation frequency
XH
Preliminary User's Manual U17260EJ3V1UD
<4> 3
Note
0
P121/X1 pin
I/O port
Crystal/ceramic resonator connection
I/O port
I/O port
Operating frequency control
s (MIN.) after AMPH has been set to 1.
If the X1 clock is used as the CPU clock, oscillation
2 1 <0>
0 0 AMPH
P122/X2/EXCLK pin
External clock input
µ
s (MIN.) after the STOP mode