NEC 78K0 Series User Manual page 417

(2) IIC status register 0 (IICS0)
This register indicates the status of I
IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait
period.
Reset signal generation sets IICS0 to 00H.
Caution If data is read from IICS0, a wait cycle is generated. Do not read data from IICS0 when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 31 CAUTIONS FOR WAIT.
Figure 17-6. Format of IIC Status Register 0 (IICS0) (1/3)
Address: FFAAH After reset: 00H
Symbol <7>
IICS0 MSTS0
MSTS0
0 Slave device status or communication standby status
1 Master device communication status
Condition for clearing (MSTS0 = 0)
• When a stop condition is detected
• When ALD0 = 1 (arbitration loss)
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
ALD0
0 This status means either that there was no arbitration or that the arbitration result was a "win".
1 This status indicates the arbitration result was a "loss". MSTS0 is cleared.
Condition for clearing (ALD0 = 0)
• Automatically cleared after IICS0 is read
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
EXC0
0 Extension code was not received.
1 Extension code was received.
Condition for clearing (EXC0 = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other
than IICS0. Therefore, when using the ALD0 bit, read the data of this bit before the data of the other
bits.
Remark LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
CHAPTER 17 SERIAL INTERFACE IIC0
2
C.
R
<6> <5> <4>
ALD0 EXC0 COI0
Master device status
Detection of arbitration loss
Note
Detection of extension code reception
Preliminary User's Manual U17260EJ3V1UD
<3> <2> <1>
TRC0 ACKD0 STD0
Condition for setting (MSTS0 = 1)
• When a start condition is generated
Condition for setting (ALD0 = 1)
• When the arbitration result is a "loss".
Condition for setting (EXC0 = 1)
• When the higher four bits of the received address data is
either "0000" or "1111" (set at the rising edge of the
eighth clock).
<0>
SPD0
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