Configuration Of Clock Output/Buzzer Output Controller; Registers Controlling Clock Output/Buzzer Output Controller - NEC 78K0 Series User Manual

12.2 Configuration of Clock Output/Buzzer Output Controller

The clock output/buzzer output controller includes the following hardware.
Table 12-1. Configuration of Clock Output/Buzzer Output Controller
Control registers

12.3 Registers Controlling Clock Output/Buzzer Output Controller

The following two registers are used to control the clock output/buzzer output controller.
• Clock output selection register (CKS)
• Port mode register 14 (PM14)
(1) Clock output selection register (CKS)
This register sets output enable/disable for clock output (PCL) and for the buzzer frequency output (BUZ), and
sets the output clock.
CKS is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets CKS to 00H.
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Item
Clock output selection register (CKS)
Port mode register 14 (PM14)
Port register 14 (P14)
Preliminary User's Manual U17260EJ3V1UD
Configuration
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