NEC 78K0 Series User Manual page 272

Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (1/2)
Count clock
Count start
00H
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
<1>
<1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than
1 clock after the operation is enabled.
<2> When the value of the 8-bit timer counter Hn matches the value of the CMP0n register, the value of the timer
counter is cleared, and the level of the TOHn output is inverted. In addition, the INTTMHn signal is output at
the rising edge of the count clock.
<3> If the TMHEn bit is cleared to 0 while timer H is operating, the INTTMHn signal and TOHn output are set to
the default level. If they are already at the default level before the TMHEn bit is cleared to 0, then that level
is maintained.
Remark n = 0, 1
01H ≤ N ≤ FEH
272
CHAPTER 9 8-BIT TIMERS H0 AND H1
(a) Basic operation (Operation When 01H ≤ CMP0n ≤ FEH)
01H
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
Preliminary User's Manual U17260EJ3V1UD
N 00H 01H
Clear
N
Interval time
<2>
N 00H 01H 00H
Clear
<3>
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear