NEC 78K0 Series User Manual page 242

(4) Timing of holding data by capture register
(a) When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n pin is detected while
CR00n/CR01n is read, CR01n performs a capture operation but the read value of CR00n/CR01n is not
guaranteed. At this time, an interrupt signal (INTTM00n/INTTM01n) is generated when the valid edge of the
TI00n/TI01n pin is detected (the interrupt signal is not generated when the reverse-phase edge of the TI00n
pin is detected).
When the count value is captured because the valid edge of the TI00n/TI01n pin was detected, read the
value of CR00n/CR01n after INTTM00n/INTTM01n is generated.
Count pulse
TM0n count value
Edge input
INTTM01n
Capture read signal
Value captured to CR01n
(b) The values of CR00n and CR01n are not guaranteed after 16-bit timer/event counter 0n stops.
(5) Setting valid edge
Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3 and TMC0n2 = 00). Set the
valid edge by using ES0n0 and ES0n1.
(6) Re-triggering one-shot pulse
Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode.
Be sure to input the next trigger after the current active level is output.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
242
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-61. Timing of Holding Data by Capture Register
N N + 1
X
Capture operation
Preliminary User's Manual U17260EJ3V1UD
N + 2 M
N + 1
Capture operation is performed
but read value is not guaranteed.
M + 1 M + 2