Configuration Of Watchdog Timer - NEC 78K0 Series User Manual

11.2 Configuration of Watchdog Timer

The watchdog timer includes the following hardware.
Control register
How the counter operation is controlled, overflow time, and window open period are set by the option byte.
Setting of Watchdog Timer
Window open period
Controlling counter operation of watchdog timer
Overflow time of watchdog timer
Remark For the option byte, see CHAPTER 25 OPTION BYTE.
CPU access signal
WDCS2 to WDCS0 of
option byte (0080H)
Clock
f /2
input
RL
controller
WINDOW1 and WINDOW0
of option byte (0080H)
WDTON of option
byte (0080H)
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CHAPTER 11 WATCHDOG TIMER
Table 11-1. Configuration of Watchdog Timer
Item
Watchdog timer enable register (WDTE)
Table 11-2. Setting of Option Bytes and Watchdog Timer
Figure 11-1. Block Diagram of Watchdog Timer
CPU access
error detector
10
2 /f
RL
17
2 /f
RL
17-bit
counter
Count clear
signal
Clear, reset control
Watchdog timer enable
register (WDTE)
Internal bus
Preliminary User's Manual U17260EJ3V1UD
Configuration
Option Byte (0080H)
Bits 6 and 5 (WINDOW1, WINDOW0)
Bit 4 (WDTON)
Bits 3 to 1 (WDCS2 to WDCS0)
to
Overflow
signal
Selector
Window size
determination
signal
Reset
Internal reset signal
output
controller