(b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 04H
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture trigger input
(TI01n)
Capture register
(CR00n)
Capture interrupt
(INTTM00n)
Capture trigger input
(TI00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
This is an application example where both the edges of the TI01n pin are detected and the count value is
captured to CR00n in the free-running timer mode.
When both CR00n and CR01n are used as capture registers and when the valid edge of only the TI01n pin is to
be detected, the count value cannot be captured to CR01n.
µ
Remark n = 0:
PD78F0531, 78F0532, 78F0533
µ
n = 0, 1:
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
218
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Figure 7-42. Timing Example of Free-Running Timer Mode
(CR00n: Capture Register, CR01n: Capture Register) (2/2)
L
00
01
0000H
L
0000H
L
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