NEC 78K0 Series User Manual page 390

(2) Serial clock selection register 1n (CSIC1n)
This register specifies the timing of the data transmission/reception and sets the serial clock.
CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
Figure 16-5. Format of Serial Clock Selection Register 10 (CSIC10)
Address: FF81H After reset: 00H R/W
Symbol 7
CSIC10 0
CKP10
0
0
1
1
CKS102
0
0
0
0
1
1
1
1
Cautions 1. Do not write to CSIC10 while CSIE10 = 1 (operation enabled).
2. To use P10/SCK10/T
status (00H).
3. The phase type of the data clock is type 1 after reset.
Remark f : Peripheral hardware clock frequency
PRS
390
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
6 5
0 0 CKP10
DAP10 Specification of data transmission/reception timing
0
SCK10
SO10
SI10 input timing
1
SCK10
SO10
SI10 input timing
0
SCK10
SO10
SI10 input timing
1
SCK10
SO10
SI10 input timing
CKS101 CKS100
0 0 f
PRS
0 1 f
PRS
1 0 f
PRS
1 1 f
PRS
0 0 f
PRS
0 1 f
PRS
1 0 f
PRS
1 1 External clock input to SCK10
D0 and P12/SO10 as general-purpose ports, set CSIC10 in the default
X
Preliminary User's Manual U17260EJ3V1UD
4 3
DAP10 CKS102
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSI10 serial clock selection
f = f = f
PRS PRS
2 MHz 5 MHz 10 MHz
/2 1 MHz 2.5 MHz 5 MHz
2
/2 500 kHz 1.25 MHz 2.5 MHz
3
/2 250 kHz 625 kHz 1.25 MHz
4
/2 125 kHz 312.5 kHz 625 kHz
5
/2 62.5 kHz 156.25 kHz 312.5 kHz
6
/2 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
7
/2 15.63 kHz 39.06 kHz 78.13 kHz
2 1
CKS101 CKS100
Type
Mode
= f =
PRS PRS
20 MHz
10 MHz Master mode
5 MHz
2.5 MHz
1.25 MHz
625 kHz
156.25 kHz
Slave mode
0
1
2
3
4