NEC 78K0 Series User Manual page 224

Figure 7-47. Example of Software Processing for PPG Output Operation
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
Timer output control bits
(TOE0n, TOC0n4, TOC0n1)
TO0n pin output
<1> Count operation start flow
START
Register initial setting
PRM0n register,
CRC0n register,
Note
TOC0n register
CR00n, CR01n registers,
port setting
TMC0n3, TMC0n2 bits = 11
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
register 0n (TOC0n).
Remarks 1. PPG pulse cycle = (M + 1) × Count clock cycle
PPG duty = (N + 1)/(M + 1)
2. n = 0:
n = 0, 1:
224
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
N
00
N + 1
M + 1
<1>
Initial setting of these
registers is performed
before setting the
, TMC0n3 and TMC0n2
bits.
Starts count operation
µ
PD78F0531, 78F0532, 78F0533
µ
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
Preliminary User's Manual U17260EJ3V1UD
M M
N
11
N
M
N + 1
M + 1
<2> Count operation stop flow
TMC0n3, TMC0n2 bits = 00
STOP
M
N
N + 1
M + 1
<2>
The counter is initialized
and counting is stopped
by clearing the TMC0n3
and TMC0n2 bits to 00.
00