NEC 78K0 Series User Manual page 332

(2) Asynchronous serial interface reception error status register 0 (ASIS0)
This register indicates an error status on completion of reception by serial interface UART0. It includes three
error flag bits (PE0, FE0, OVE0).
This register is read-only by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0. 00H is read
when this register is read. If a reception error occurs, read ASIS0 and then read receive buffer register 0 (RXB0)
to clear the error flag.
Figure 14-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)
Address: FF73H After reset: 00H R
Symbol 7
ASIS0 0
PE0
0
1
FE0
0
1
OVE0
0
1
Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of
asynchronous serial interface operation mode register 0 (ASIM0).
2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of
stop bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 0
(RXB0) but discarded.
4. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 31 CAUTIONS FOR WAIT.
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CHAPTER 14 SERIAL INTERFACE UART0
6 5
0 0
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
If the parity of transmit data does not match the parity bit on completion of reception.
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
If the stop bit is not detected on completion of reception.
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
If receive data is set to the RXB0 register and the next reception operation is completed before the
data is read.
Preliminary User's Manual U17260EJ3V1UD
4 3
0 0 PE0
Status flag indicating parity error
Status flag indicating framing error
Status flag indicating overrun error
2 1 0
FE0 OVE0