NEC 78K0 Series User Manual page 206

(4) Operation in clear & start mode entered by TI00n pin valid edge input
(CR00n: capture register, CR01n: capture register)
Figure 7-33. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Capture Register)
Count clock
Edge
TI00n pin
detection
Edge
Note
TI01n pin
detection
Note The timer output (TO0n) cannot be used when detecting the valid edge of the TI01n pin is used.
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
206
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Operable bits
TMC0n3, TMC0n2
Capture signal
Capture
signal
Preliminary User's Manual U17260EJ3V1UD
Clear
Timer counter
(TM0n)
Capture register
(CR01n)
Capture register
(CR00n)
Interrupt signal
(INTTM01n)
Output
Note
TO0n pin
controller
Interrupt signal
(INTTM00n)