NEC 78K0 Series User Manual page 203

(3) Operation in clear & start mode by entered TI00n pin valid edge input
(CR00n: capture register, CR01n: compare register)
Figure 7-31. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Compare Register)
TI00n pin
Count clock
Operable bits
TMC0n3, TMC0n2
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Edge
detection
Timer counter
(TM0n)
Capture register
Capture signal
(CR00n)
Preliminary User's Manual U17260EJ3V1UD
Clear
Match signal
Compare register
Output
(CR01n) controller
Interrupt signal
(INTTM01n)
TO0n pin
Interrupt signal
(INTTM00n)
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