NEC 78K0 Series User Manual page 431

(2) When master and slave devices both have a nine-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Master
IIC0
SCL0
Slave
IIC0
SCL0
H
ACKE0
Transfer lines
SCL0
SDA0
Generate according to previously set ACKE0 value
Remark ACKE0: Bit 2 of IIC control register 0 (IICC0)
WREL0: Bit 5 of IIC control register 0 (IICC0)
A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0).
Normally, the receiving side cancels the wait state when bit 5 (WREL0) of IICC0 is set to 1 or when FFH is written
to IIC shift register 0 (IIC0), and the transmitting side cancels the wait state when data is written to IIC0.
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STT0) of IICC0 to 1
• By setting bit 0 (SPT0) of IICC0 to 1
CHAPTER 17 SERIAL INTERFACE IIC0
Figure 17-18. Wait (2/2)
Master and slave both wait
after output of ninth clock
6 7 8 9
Wait from
master and
slave
6 7 8 9
D2 D1 D0 ACK
Preliminary User's Manual U17260EJ3V1UD
IIC0 data write (cancel wait)
1 2 3
FFH is written to IIC0 or WREL0 is set to 1
Wait from slave
1 2 3
D7 D6 D5
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