NEC 78K0 Series User Manual page 407

SDA0/
P61
Noise
eliminator
DFC0
N-ch open-
drain output
Output latch
PM61
(P61)
SCL0/
P60
Noise
eliminator
DFC0
N-ch open-
drain output
Output latch
PM60
(P60)
CHAPTER 17 SERIAL INTERFACE IIC0
Figure 17-1. Block Diagram of Serial Interface IIC0
Internal bus
IIC control register 0 (IICC0)
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
Slave address
Clear
register 0 (SVA0)
Set
Match
signal
SO latch
IIC shift
D Q
CL01,
register 0 (IIC0)
CL00
Data hold
TRC0
time correction
circuit
Output control
ACK detector
Start condition
detector
Stop condition
detector
Serial clock
counter
Serial clock
controller
f
PRS
Prescaler
EXSCL0/
P62
CLD0 DAD0 SMC0 DFC0 CL01 CL00
Preliminary User's Manual U17260EJ3V1UD
IIC status register 0 (IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
Start
condition
generator
Stop
condition
generator
ACK
generator
Interrupt request
signal generator
IICS0.MSTS0,
EXC0, COI0
Serial clock
wait controller
IIC shift register 0 (IIC0)
IICC0.STT0, SPT0
IICS0.MSTS0, EXC0, COI0
CLX0
IIC clock selection IIC function expansion
register 0 (IICCL0)
register 0 (IICX0)
Internal bus
Wake-up
controller
INTIIC0
Bus status
detector
STCF IICBSY STCEN IICRSV
IIC flag register 0
(IICF0)
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