NEC 78K0 Series User Manual page 192

Figure 7-22. Example of Register Settings for Square Wave Output Operation
(a) 16-bit timer mode control register 0n (TMC0n)
0 0
(b) Capture/compare control register 0n (CRC0n)
0 0
(c) 16-bit timer output control register 0n (TOC0n)
OSPT0n OSPE0n
0 0
(d) Prescaler mode register 0n (PRM0n)
ES1n1 ES1n0 ES0n1
0 0
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
If M is set to CR00n, the interval time is as follows.
• Square wave frequency = 1 / [2 × (M + 1) × Count clock cycle]
Setting CR00n to 0000H is prohibited.
(g) 16-bit capture/compare register 01n (CR01n)
Usually, CR01n is not used for the square wave output function. However, a compare match interrupt
(INTTM01n) is generated when the set value of CR01n matches the value of TM0n.
Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n).
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
192
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
TMC0n3 TMC0n2 TMC0n1
0 0 1
CRC0n2 CRC0n1 CRC0n0
0 0 0
TOC0n4 LVS0n
0 0 0
ES0n0 3
0 0 0
Preliminary User's Manual U17260EJ3V1UD
OVF0n
1 0 0
Clears and starts on match
between TM0n and CR00n.
0 0 0
CR00n used as
compare register
LVR0n TOC0n1 TOE0n
0 1 1
2 PRM0n1 PRM0n0
0 0/1 0/1
Enables TO0n pin output.
Inverts TO0n pin output on match
between TM0n and CR00n.
Selects count clock