NEC 78K0 Series User Manual page 142

(5) Main OSC control register (MOC)
This register selects the operation mode of the high-speed system clock.
This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the
CPU operates with a clock other than the high-speed system clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 80H.
Address: FFA2H After reset: 80H
Symbol <7>
MOC MSTOP
MSTOP
0
1
Cautions 1. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock
142
CHAPTER 6 CLOCK GENERATOR
Figure 6-5. Format of Main OSC Control Register (MOC)
R/W
6 5
0 0
Control of high-speed system clock operation
X1 oscillation mode
X1 oscillator operating
X1 oscillator stopped
other than the high-speed system clock. Specifically, set under either of the
following conditions.
• When MCS = 0 (when CPU operates with the internal high-speed oscillation
clock)
• When CLS = 1 (when CPU operates with the subsystem clock)
In addition, stop peripheral hardware that is operating on the high-speed system
clock before setting MSTOP to 1.
2. Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select
register (OSCCTL) is 0 (I/O port mode).
3. The peripheral hardware cannot operate when the peripheral hardware clock is
stopped. To resume the operation of the peripheral hardware after the
peripheral hardware clock has been stopped, initialize the peripheral hardware.
Preliminary User's Manual U17260EJ3V1UD
4 3 2
0 0 0
External clock input mode
External clock from EXCLK pin is enabled
External clock from EXCLK pin is disabled
1 0
0 0