NEC 78K0 Series User Manual page 533

Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
V
LVI
Supply voltage 2.7 V (TYP.)
(V )
DD
Note 1
1.8 V
V = 1.59 V (TYP.)
POC
0 V
Internal high-speed
oscillation clock (f )
RH
High-speed
system clock (f )
XH
(when X1 oscillation
is selected)
Operation
CPU
stops
Internal reset signal
The operation guaranteed range is 1.8 V ≤ V
Notes 1.
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
2. The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 24
LOW-VOLTAGE DETECTOR).
Remark V : LVI detection voltage
LVI
V : POC detection voltage
POC
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
and Low-Voltage Detector (2/2)
Set LVI to be
used for reset
Wait for oscillation
accuracy
stabilization
Starting oscillation is
specified by software.
Reset period
Normal operation
(oscillation
(internal high-speed
Note 2 stop)
oscillation clock)
µ
Reset processing (20 s (TYP.)) Reset processing (20 s (TYP.))
Preliminary User's Manual U17260EJ3V1UD
Set LVI to be
used for interrupt
Wait for oscillation
Wait for oscillation
accuracy
accuracy
stabilization
stabilization
Starting oscillation is
specified by software.
Normal operation Reset period
(oscillation
(internal high-speed
Note 2 stop)
oscillation clock)
µ
Reset processing (20 s (TYP.))
≤ 5.5 V. To make the state at lower than 1.8 V reset
DD
Set LVI to be
used for reset
Starting oscillation is
specified by software.
Normal operation
(internal high-speed
Note 2
oscillation clock)
Operation stops
µ
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