NEC 78K0 Series User Manual page 165

Table 6-5. CPU Clock Transition and SFR Register Setting Examples (4/4)
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(D) → (C) (X1 clock: 1 MHz ≤ f
10 MHz)
(D) → (C) (external main clock: 1 MHz ≤
≤ 10 MHz
f
XH
(D) → (C) (X1 clock: 10 MHz < f
20 MHz)
(D) → (C) (external main clock: 10 MHz <
≤ 20 MHz)
f
XH
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
already been set.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET)).
(10) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
Status Transition
(B) → (E)
(C) → (F)
(D) → (G)
(11) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
Status Transition
(B) → (H)
(C) → (I)
Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14.
2. EXCLK, OSCSEL, AMPH: Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL)
MSTOP:
XSEL, MCM0:
CSS:
CHAPTER 6 CLOCK GENERATOR
Note
AMPH EXCLK
≤
0 0
XH
0 1
≤
1 0
XH
1 1
Unnecessary if these registers
are already set
Executing HALT instruction
(Setting sequence)
Stopping peripheral functions that
cannot operate in STOP mode
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Bit 4 of the processor clock control register (PCC)
Preliminary User's Manual U17260EJ3V1UD
OSCSEL MSTOP OSTC
Register
1 0 Must be
checked
1 0
Must not be
checked
Must be
1 0
checked
1 0
Must not be
checked
Unnecessary if the
CPU is operating
with the high-speed
system clock
Setting
Setting
Executing STOP instruction
Note
XSEL MCM0 CSS
1 1 0
1 1 0
1 1 0
1 1 0
Unnecessary if this register
is already set
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