Registers Controlling Serial Interface Uart6 - NEC 78K0 Series User Manual

8-bit single-chip microcontrollers
Hide thumbs Also See for 78K0 Series:
Table of Contents

Advertisement

15.3 Registers Controlling Serial Interface UART6

Serial interface UART6 is controlled by the following nine registers.
• Asynchronous serial interface operation mode register 6 (ASIM6)
• Asynchronous serial interface reception error status register 6 (ASIS6)
• Asynchronous serial interface transmission status register 6 (ASIF6)
• Clock selection register 6 (CKSR6)
• Baud rate generator control register 6 (BRGC6)
• Asynchronous serial interface control register 6 (ASICL6)
• Input switch control register (ISC)
• Port mode register 1 (PM1)
• Port register 1 (P1)
(1) Asynchronous serial interface operation mode register 6 (ASIM6)
This 8-bit register controls the serial communication operations of serial interface UART6.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)
Address: FF50H After reset: 01H R/W
Symbol
<7>
ASIM6
POWER6
POWER6
Note 1
0
1
TXE6
0
1
RXE6
0
1
Notes 1.
The output of the T
when POWER6 = 0 during transmission.
2.
Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
354
CHAPTER 15 SERIAL INTERFACE UART6
<6>
<5>
TXE6
RXE6
Enables/disables operation of internal operation clock
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
Note 2
resets the internal circuit
.
Enables operation of the internal operation clock
Disables transmission (synchronously resets the transmission circuit).
Enables transmission
Disables reception (synchronously resets the reception circuit).
Enables reception
D6 pin goes high level and the input from the R
X
Preliminary User's Manual U17260EJ3V1UD
4
3
PS61
PS60
CL6
Enables/disables transmission
Enables/disables reception
2
1
0
SL6
ISRM6
D6 pin is fixed to the high level
X

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents