External Event Counter Operation - NEC 78K0 Series User Manual

7.4.3 External event counter operation

When bits 1 and 0 (PRM0n1 and PRM0n0) of the prescaler mode register 0n (PRM0n) are set to 11 (for counting
up with the valid edge of the TI00n pin) and bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register
0n (TMC0n) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating
matching between TM0n and CR00n (INTTM00n) is generated.
To input the external event, the TI00n pin is used. Therefore, the timer/event counter cannot be used as an
external event counter in the clear & start mode entered by the TI00n pin valid edge input (when TMC0n3 and
TMC0n2 = 10).
The INTTM00n signal is generated with the following timing.
• Timing of generation of INTTM00n signal (second time or later)
= Number of times of detection of valid edge of external event × (Set value of CR00n + 1)
However, the first match interrupt immediately after the timer/event counter has started operating is generated with
the following timing.
• Timing of generation of INTTM00n signal (first time only)
= Number of times of detection of valid edge of external event input × (Set value of CR00n + 2)
To detect the valid edge, the signal input to the TI00n pin is sampled during the clock cycle of f
is not detected until it is detected two times in a row. Therefore, a noise with a short pulse width can be eliminated.
Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS.
Figure 7-24. Block Diagram of External Event Counter Operation
f
PRS
Edge
TI00n pin
detection
TMC0n3, TMC0n2
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
194
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
16-bit counter (TM0n)
Operable bits
Preliminary User's Manual U17260EJ3V1UD
Clear
Match signal
CR00n register
. The valid edge
PRS
Output
TO0n pin
controller
INTTM00n signal