NEC 78K0 Series User Manual page 200

(2) Operation in clear & start mode entered by TI00n pin valid edge input
(CR00n: compare register, CR01n: capture register)
Figure 7-29. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
TI00n pin
Count clock
Operable bits
TMC0n3, TMC0n2
µ
Remark n = 0: PD78F0531, 78F0532, 78F0533
µ
n = 0, 1: PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
200
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
(CR00n: Compare Register, CR01n: Capture Register)
Edge
detector
Timer counter
(TM0n)
Capture register
Capture signal
(CR01n)
Preliminary User's Manual U17260EJ3V1UD
Clear
Match signal
Compare register
Output
(CR00n)
controller
Interrupt signal
(INTTM00n)
TO0n pin
Interrupt signal
(INTTM01n)