CHAPTER 3 CPU ARCHITECTURE
Figure 3-19. Data to Be Saved to Stack Memory
(a) PUSH rp instruction (when SP = FEE0H)
FEE0H
SP
SP
FEDEH
(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)
SP
FEE0H
SP
FEDEH
(c) Interrupt, BRK instructions (when SP = FEE0H)
SP
FEE0H
FEDDH
SP
Preliminary User's Manual U17260EJ3V1UD
FEE0H
FEDFH
Register pair higher
FEDEH
Register pair lower
FEE0H
FEDFH
PC15 to PC8
FEDEH
PC7 to PC0
FEE0H
FEDFH
PSW
FEDEH
PC15 to PC8
FEDDH
PC7 to PC0
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