NEC 78K0 Series User Manual page 410

(3) SO latch
The SO latch is used to retain the SDA0 pin's output level.
(4) Wake-up controller
This circuit generates an interrupt request (INTIIC0) when the address received by this register matches the
address value set to slave address register 0 (SVA0) or when an extension code is received.
(5) Prescaler
This selects the sampling clock to be used.
(6) Serial clock counter
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to
verify that 8-bit data was transmitted or received.
(7) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIIC0).
2
An I C interrupt request is generated by the following two triggers.
• Falling edge of eighth or ninth clock of the serial clock (set by WTIM0 bit)
• Interrupt request generated when a stop condition is detected (set by SPIE0 bit)
Remark WTIM0 bit: Bit 3 of IIC control register 0 (IICC0)
SPIE0 bit: Bit 4 of IIC control register 0 (IICC0)
(8) Serial clock controller
In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock.
(9) Serial clock wait controller
This circuit controls the wait timing.
(10) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits generate and detect each status.
(11) Data hold time correction circuit
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
(12) Start condition generator
This circuit generates a start condition when the STT0 bit is set to 1.
However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released
(IICBSY bit = 1), start condition requests are ignored and the STCF bit is set to 1.
(13) Stop condition generator
This circuit generates a stop condition when the SPT0 bit is set to 1.
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CHAPTER 17 SERIAL INTERFACE IIC0
Preliminary User's Manual U17260EJ3V1UD