NEC 78K0 Series User Manual page 413

8-bit single-chip microcontrollers
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Address: FFA6H
After reset: 00H
Symbol
<7>
<6>
IICC0
IICE0
LREL0
IICE0
0
Stop operation. Reset IIC status register 0 (IICS0)
1
Enable operation.
Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level.
Condition for clearing (IICE0 = 0)
• Cleared by instruction
• Reset
Note 2
LREL0
0
Normal operation
1
This exits from the current communications and sets standby mode. This setting is automatically cleared to 0
after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL0 and SDA0 lines are set to high impedance.
The following flags of IIC control register 0 (IICC0) and IIC status register 0 (IICS0) are cleared to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
The standby mode following exit from communications remains in effect until the following communications entry conditions
are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0)
• Automatically cleared after execution
• Reset
Note 2
WREL0
0
Do not cancel wait
1
Cancel wait. This setting is automatically cleared after wait is canceled.
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 = 1), the
SDA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0)
• Automatically cleared after execution
• Reset
Notes 1. The IICS0 register, the STCF0 and IICBSY bits of the IICF0 register, and the CLD0 and DAD0 bits of the
IICCL0 register are reset.
2. This flag's signal is invalid when IICE0 = 0.
Caution The start condition is detected immediately after I
SCL0 line is at high level and the SDA0 line is at low level. Immediately after enabling I
operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory manipulation instruction.
CHAPTER 17 SERIAL INTERFACE IIC0
Figure 17-5. Format of IIC Control Register 0 (IICC0) (1/4)
R/W
<5>
<4>
WREL0
SPIE0
Exit from communications
Preliminary User's Manual U17260EJ3V1UD
<3>
<2>
<1>
WTIM0
ACKE0
STT0
2
I
C operation enable
Note 1
. Stop internal operation.
Condition for setting (IICE0 = 1)
• Set by instruction
Condition for setting (LREL0 = 1)
• Set by instruction
Wait cancellation
Condition for setting (WREL0 = 1)
• Set by instruction
2
C is enabled to operate (IICE0 = 1) while the
<0>
SPT0
2
C to
413

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