NEC 78K0 Series User Manual page 333

(3) Baud rate generator control register 0 (BRGC0)
This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.
BRGC0 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 1FH.
Figure 14-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
Address: FF71H After reset: 1FH R/W
Symbol 7
BRGC0 TPS01
TPS01
0
0
1
1
MDL04
0
0
0
0
•
•
•
•
•
1
1
1
1
1
1
Note Note the following points when selecting the TM50 output as the base clock.
• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation
(TMC501 = 1).
• PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
It is not necessary to enable the TO50 pin as a timer output pin in any mode.
CHAPTER 14 SERIAL INTERFACE UART0
6 5
TPS00 0 MDL04
TPS00
f
PRS
Note
0 TM50 output
1 f /2 1 MHz
PRS
3
0 f /2 250 kHz
PRS
5
1 f /2 62.5 kHz
PRS
MDL03 MDL02 MDL01
×
0
1 0
1 0
1 0
• •
• •
• •
• •
• •
1 0
1 0
1 1
1 1
1 1
1 1
Preliminary User's Manual U17260EJ3V1UD
4 3 2
MDL03 MDL02
Base clock (f ) selection
XCLK0
= 2 MHz f = 5 MHz
PRS
2.5 MHz
625 kHz
156.25 kHz
MDL00 k
× × ×
Setting prohibited
0 0 8 f
XCLK0
0 1 9 f
XCLK0
1 0 10 f
XCLK0
• • •
• • •
• • •
• • •
• • •
1 0 26 f
XCLK0
1 1 27 f
XCLK0
0 0 28 f
XCLK0
0 1 29 f
XCLK0
1 0 30 f
XCLK0
1 1 31 f
XCLK0
1 0
MDL01 MDL00
f = 10 MHz f = 20 MHz
PRS PRS
5 MHz 10 MHz
1.25 MHz 2.5 MHz
312.5 kHz 625 kHz
Selection of 5-bit counter
output clock
/8
/9
/10
•
•
•
•
•
/26
/27
/28
/29
/30
/31
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