Canceling Wait; Interrupt Request (Intiic0) Generation Timing And Wait Control - NEC 78K0 Series User Manual

17.5.7 Canceling wait

2
The I C usually cancels a wait state by the following processing.
• Writing data to IIC shift register 0 (IIC0)
• Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait)
• Setting bit 1 (STT0) of IIC0 register (generating start condition)
• Setting bit 0 (SPT0) of IIC0 register (generating stop condition)
Note Master only
When the above wait canceling processing is executed, the I
resumed.
To cancel a wait state and transmit data (including addresses), write the data to IIC0.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IIC0 control
register 0 (IICC0) to 1.
To generate a restart condition after canceling a wait state, set bit 1 (STT0) of IICC0 to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of IICC0 to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to IIC0 after canceling a wait state by setting WREL0 to 1, an incorrect value may be
output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IIC0.
In addition to the above, communication is stopped if IICE0 is cleared to 0 when communication has been aborted,
so that the wait state can be canceled.
2
If the I C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of
IICC0, so that the wait state can be canceled.

17.5.8 Interrupt request (INTIIC0) generation timing and wait control

The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated
and the corresponding wait control, as shown in Table 17-3.
WTIM0 During Slave Device Operation
Address
Notes 1, 2
0 9
Notes 1, 2
1 9
Notes 1. The slave device's INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to slave address register 0 (SVA0).
At this point, ACK is generated regardless of the value set to IICC0's bit 2 (ACKE0). For a slave device
that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIIC0 is generated at the falling edge of the 9th
clock, but wait does not occur.
2. If the received address does not match the contents of slave address register 0 (SVA0) and extension
code is not received, neither INTIIC0 nor a wait occurs.
Remark The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and
wait control are both synchronized with the falling edge of these clock signals.
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CHAPTER 17 SERIAL INTERFACE IIC0
Table 17-3. INTIIC0 Generation Timing and Wait Control
Data Reception Data Transmission
Note 2 Note 2
8 8
Note 2 Note 2
9 9
Preliminary User's Manual U17260EJ3V1UD
Note
Note
2
C cancels the wait state and communication is
During Master Device Operation
Address Data Reception
9 8
9 9
Data Transmission
8
9