NEC 78K0 Series User Manual page 515

(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
(1) When high-speed system clock is used as CPU clock
Reset signal
Normal operation
Status of CPU system clock)
High-speed
system clock
(X1 oscillation)
(2) When internal high-speed oscillation clock is used as CPU clock
Reset signal
Normal operation
(internal high-speed
oscillation clock)
Status of CPU
Internal high-speed
oscillation clock
Reset signal
Normal operation
Status of CPU (subsystem clock)
Subsystem clock
(XT1 oscillation)
Remark f : X1 clock oscillation frequency
X
CHAPTER 21 STANDBY FUNCTION
Figure 21-4. HALT Mode Release by Reset
HALT
instruction
(high-speed
HALT mode
Oscillates
HALT
instruction
HALT mode
Oscillates
(3) When subsystem clock is used as CPU clock
HALT
instruction
HALT mode
Oscillates
Preliminary User's Manual U17260EJ3V1UD
Reset
Normal operation
processing
(internal high-speed
Reset
µ
(20 s (TYP.))
oscillation clock)
period
Oscillation Oscillation
stopped stopped
Oscillates
Oscillation stabilization time
11
(2 /f
X
Starting X1 oscillation is
specified by software.
Reset
Normal operation
processing (internal high-speed
Reset
µ
period oscillation clock)
(20 s (TYP.))
Oscillation
stopped
Oscillates
Wait for oscillation
accuracy stabilization
Reset
Normal operation mode
processing
Reset (internal high-speed
µ
period (20 s (TYP.))
oscillation clock)
Oscillation
Oscillation
stopped
stopped
Oscillates
Starting XT1 oscillation is
specified by software.
16
to 2 /f )
X
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