0X0020 08A0-0X0020 08A8 Hw Processor (Hwp); 0X0020 1000-0X0020 2014 Dma Controller (Dmac) - Epson S1C31D50 Technical Manual

0x0020 08a0–0x0020 08a8
Address Register name
0x0020 HWPCTL
08a2 (HWP Control
Register)
0x0020 HWPINTF
08a4 (HWP Interrupt Flag
Register)
0x0020 HWPINTE
08a6 (HWP Interrupt
Enable Register)
0x0020 HWPCMDTRG
08a8 (HWP Command Trig-
ger Register)
0x0020 1000–0x0020 2014
Address Register name
0x0020 DMACSTAT
1000
(DMAC Status
Register)
0x0020 DMACCFG
1004
(DMAC Configuration
Register)
0x0020 DMACCPTR
1008 (DMAC Control Data
Base Pointer Register)
0x0020 DMACACPTR
100c (DMAC Alternate
Control Data Base
Pointer Register)
0x0020 DMACSWREQ
1014 (DMAC Software
Request Register)
0x0020 DMACRMSET
1020
(DMAC Request
Mask Set Register)
0x0020 DMACRMCLR
1024 (DMAC Request
Mask Clear Register)
0x0020 DMACENSET
1028 (DMAC Enable Set
Register)
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Bit Bit name
15–8 –
7–1 –
0 HWPEN
15–8 –
7–2 –
1 HWP1IF
0 HWP0IF
15–8 –
7–1 –
0 HWPIE
15–8 –
7–1 –
0 HWP0TRG
Bit Bit name
31–24 –
23–21 –
20–16 CHNLS[4:0]
15–8 –
7–4 STATE[3:0]
3–1 –
0 MSTENSTAT
31–24 –
23–16 –
15–8 –
7–1 –
0 MSTEN
31–7 CPTR[31:7]
6–0 CPTR[6:0]
31–0 ACPTR[31:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 SWREQ[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 RMSET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 RMCLR[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 ENSET[3:0]
Seiko Epson Corporation
HW Processor (HWP)
Initial Reset R/W
0x00 – R
0x00 – R
0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
DMA Controller (DMAC)
Initial Reset R/W
0x00 – R
0x0 – R
H0 R
*
0x00 – R
0x0 H0 R
0x0 – R
0 H0 R
0x00 – R
0x00 – R
0x00 – R
0x00 – R
– – W
0x000 H0 R/W
0000
0x00 H0 R
– H0 R
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
Remarks
–
–
Cleared by writing 0.
–
–
Remarks
–
* Number of channels
implemented - 1
–
–
–
–
–
–
–
–
AP-A-53