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21 HW Processor (HWP) and Sound Output
21.7 Control Registers
HWP Control Register
Register name
Bit
HWPCTL
15–8 –
7–1 –
0
Bits 15–1 Reserved
Bit 0
HWPEN
This bit enables the HWP operations.
1 (R/W): Enable HWP operations (The operating clock is supplied.)
0 (R/W): Disable HWP operations (The operating clock is stopped.)
HWP Interrupt Flag Register
Register name
Bit
HWPINTF
15–8 –
7–2 –
1
0
Bits 15–2 Reserved
Bit 1
HWP1IF
Bit 0
HWP0IF
These bits indicate the HWP interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Setting prohibited
0 (W):
Clear flag
The following shows the correspondence between the bit and interrupt:
HWPINTF.HWP1IF bit: Error occurrence interrupt
HWPINTF.HWP0IF bit: State transition interrupt
Note: Be aware that the writing value to clear the flags is different from other peripheral circuits.
HWP Interrupt Enable Register
Register name
Bit
HWPINTE
15–8 –
7–1 –
0
Bits 15–1 Reserved
Bit 0
HWPIE
This bit enables HWP interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
HWP Command Trigger Register
Register name
Bit
HWPCMDTRG
15–8 –
7–1 –
0
Bits 15–1 Reserved
21-26
Bit name
Initial
0x00
0x00
HWPEN
0
Bit name
Initial
0x00
0x00
HWP1IF
0
HWP0IF
0
Bit name
Initial
0x00
0x00
HWPIE
0
Bit name
Initial
0x00
0x00
HWP0TRG
0
Seiko Epson Corporation
Reset
R/W
–
R
–
–
R
H0
R/W
Reset
R/W
–
R
–
–
R
H0
R/W
Cleared by writing 0.
H0
R/W
Reset
R/W
–
R
–
–
R
H0
R/W
Reset
R/W
–
R
–
–
R
H0
R/W
S1C31D50/D51 TECHNICAL MANUAL
Remarks
Remarks
Remarks
Remarks
(Rev. 2.00)
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