Pa Port Group - Epson S1C31D50 Technical Manual

Cmos 32-bit single chip
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Register name
Bit
P9FNCSEL
15–12 –
(P9 Port Function
11–10 P95MUX[1:0]
Select Register)
9–8 P94MUX[1:0]
7–6 P93MUX[1:0]
5–4 P92MUX[1:0]
3–2 P91MUX[1:0]
1–0 P90MUX[1:0]
P9SELy = 0
Port
P9yMUX = 0x0
name
GPIO
(Function 0)
Peripheral
P90
P90
QSPI Ch.0 QSPICLK0
P91
P91
QSPI Ch.0 QSDIO00
P92
P92
QSPI Ch.0 QSDIO01
P93
P93
QSPI Ch.0 QSDIO02
P94
P94
QSPI Ch.0 QSDIO03
P95
P95
QSPI Ch.0 #QSPISS0

7.7.11 Pa Port Group

The Pa port group supports the GPIO and interrupt functions.
Register name
Bit
PADAT
15
(Pa Port Data
14
Register)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAIOEN
15
(Pa Port Enable
14
Register)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name
Initial
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Table 7.7.10.2 P9 Port Group Function Assignment
P9yMUX = 0x1
(Function 1)
Pin
Peripheral
Table 7.7.11.1 Control Registers for Pa Port Group
Bit name
Initial
0
PAOUT6
0
PAOUT5
0
PAOUT4
0
PAOUT3
0
PAOUT2
0
PAOUT1
0
PAOUT0
0
0
PAIN6
0
PAIN5
0
PAIN4
0
PAIN3
0
PAIN2
0
PAIN1
0
PAIN0
0
0
PAIEN6
0
PAIEN5
0
PAIEN4
0
PAIEN3
0
PAIEN2
0
PAIEN1
0
PAIEN0
0
0
PAOEN6
0
PAOEN5
0
PAOEN4
0
PAOEN3
0
PAOEN2
0
PAOEN1
0
PAOEN0
0
Seiko Epson Corporation
Reset
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
P9SELy = 1
P9yMUX = 0x2
(Function 2)
Pin
Peripheral
Pin
Reset
R/W
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
R
H0
R
H0
R
H0
R
H0
R
H0
R
H0
R
H0
R
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
7 I/O PORTS (PPORT)
48
64
Remarks
pin
pin
P9yMUX = 0x3
48
64
(Function 3)
pin
pin
Peripheral
Pin
48
64
Remarks
pin
pin
80
100
pin
pin
80
100
pin
pin
80
100
pin
pin
7-35

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