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Bits 7–4
SVDRE[3:0]
These bits enable/disable the reset issuance function when a low power supply voltage is detected.
0xa (R/WP):
Other than 0xa (R/WP): Disable (Generate interrupt)
For more information on the SVD3 reset issuance function, refer to "SVD3 Reset."
Bit 3
EXSEL
This bit selects the voltage to be detected when the SVD3CTL.VDSEL bit = 1.
1 (R/WP): EXSVD1
0 (R/WP): EXSVD0
Bits 2–1
SVDMD[1:0]
These bits select intermittent operation mode and its detection cycle.
Table 11.6.4 Intermittent Operation Mode Detection Cycle Selection
SVD3CTL.SVDMD[1:0] bits
For more information on intermittent and continuous operation modes, refer to "SVD3 Operations."
Bit 0
MODEN
This bit enables/disables for the SVD3 circuit to operate.
1 (R/WP): Enable (Start detection operations)
0 (R/WP): Disable (Stop detection operations)
After this bit has been altered, wait until the value written is read out from this bit without subsequent
operations being performed.
Notes: • Writing 0 to the SVD3CTL.MODEN bit resets the SVD3 hardware. However, the register val-
ues set and the interrupt flag are not cleared. The SVD3CTL.MODEN bit is actually set to 0
after this processing has finished. If 1 is written to the SVD3CTL.MODEN bit continuously
without waiting for the bit being read as 0 at this time, writing 0 may be ignored and a mal-
function may occur as the hardware restarts without resetting.
• The SVD3 internal circuit is initialized if the SVD3CTL.SVDSC[1:0] bits, SVD3CTL.SVDRE[3:0]
bits, or SVD3CTL.SVDMD[1:0] bits are altered while SVD3 is in operation after 1 is written to
the SVD3CTL.MODEN bit.
SVD3 Status and Interrupt Flag Register
Register name
Bit
SVD3INTF
15–9 –
8
7–1 –
0
Bits 15–9 Reserved
Bit 8
SVDDT
The power supply voltage detection results can be read out from this bit.
1 (R):
Power supply voltage (V
0 (R):
Power supply voltage (V
Bits 7–1
Reserved
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Enable (Issue reset)
0x3
Intermittent operation mode (CLK_SVD3/512)
0x2
Intermittent operation mode (CLK_SVD3/256)
0x1
Intermittent operation mode (CLK_SVD3/128)
0x0
Bit name
Initial
0x00
SVDDT
x
0x00
SVDIF
0
, EXSVDn) < SVD detection voltage V
DD
, EXSVDn) ≥ SVD detection voltage V
DD
Seiko Epson Corporation
11 SUPPLY VOLTAGE DETECTOR (SVD3)
Operation mode (detection cycle)
Continuous operation mode
Reset
R/W
–
R
–
–
R
–
R
H1
R/W
Cleared by writing 1.
or EXSVD detection voltage V
or EXSVD detection voltage V
Remarks
SVD
SVD_EXT
SVD
SVD_EXT
11-7
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