Sdac Clock Control Register; Sdac Control Register - Epson S1C31D50 Technical Manual

Bit 0 HWP0TRG
This bit starts executing the command specified by the HWP internal register.
1 (W): Trigger to issue command
0 (W): Setting prohibited
1 (R): In command issuing process
0 (R): Command issuance completed/standby to issue command

SDAC Clock Control Register

Register name Bit
SDACCLK 15–9 –
8
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the SDAC operating clock is supplied in DEBUG mode or not.
1 (R/W): Clock supplied in DEBUG mode
0 (R/W): No clock supplied in DEBUG mode
Bits 7–6 Reserved
Bits 5–4 CLKDIV[1:0]
These bits select the division ratio of the SDAC operating clock.
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of SDAC.
SDACCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note: The SDACCLK register settings can be altered only when the SDACCTL.SDACEN bit = 0.

SDAC Control Register

Register name Bit
SDACCTL 15–8 –
7–1 –
0
Bits 15–1 Reserved
Bit 0 SDACEN
This bit enables the SDAC operations.
1 (R/W): Enable SDAC operations (The operating clock is supplied.)
0 (R/W): Disable SDAC operations (The operating clock is stopped.)
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0x0
0x0
Table 21.7.1 Clock Source and Division Ratio Settings
0x0
IOSC
Reserved
1/1
Bit name Initial
0x00
0x00
SDACEN 0
Seiko Epson Corporation
21 HW Processor (HWP) and Sound Output
Reset R/W
– R –
H0 R/W
– R
H0 R/W
– R
H0 R/W
SDACCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
Reserved
Reserved
1/1
Reset R/W
– R –
– R
H0 R/W
Remarks
0x3
EXOSC
Reserved
1/1
Remarks
21-27